1. Field of the Invention
The present invention relates to a variable delay circuit which is capable of setting delay time to a predetermined value. Especially, this invention relates to a technology for reducing power consumption of the variable delay circuit.
2. Description of the Related Art
FIG. 1 shows a variable delay circuit of the prior art.
The variable delay circuit has a delay circuit 2 in which delay stages. 2a are connected in cascade and a selector 4. The delay circuit 2 receives an input signal IN at the initial delay stage 2a and outputs delayed signals DT1, DT2, . . . , DTnxe2x88x921, DTn from each of the delay stages 2a, respectively. Hereinafter, the delayed signals DT0 to DTn are also referred to as the delayed signal DT, collectively. The selector 4 receives the delayed signals DT0, DT1, . . . , DTnxe2x88x921, DTn and selecting signals SS0, SS1, . . . ,SSnxe2x88x921, SSn which correspond to the delayed signals DT like the above, respectively. Hereinafter, the selecting signals SS0 to SSn are also referred to as the selecting signal SS, collectively. The selecting signals SS are outputted from a not-shown control circuit and any of these is activated. The selector 4 selects the delayed signal DT which corresponds to the activated selecting signal SS and outputs the selected delayed signal DT as a delayed output signal OUT. As a result, the variable delay circuit operates as the circuit which delays the input signal IN by a predetermined time according to the selecting signal SS.
Note that, when the aforesaid variable delay circuit receives a change of the input signal IN, it transmits the change of the input signal IN by successively operating all of the delay stages 2a. For example, when the selector 4 receives the activation of the selecting signal SS1 to select the delayed signal DT1, the delay stages 2a subsequent to the delay stage 2a which outputs the delayed signal DT1 successively output the delayed signal DT2, DT3, . . . , DTn. Thus, the variable delay circuit of the prior art has a problem of wastefully consuming power because the unnecessary delay stages 2a are operated. Especially, when increasing a change amount of delay time or setting the delay time at smaller intervals, it is necessary to increase the delay stages 2a in number, in which case the power consumption of the variable delay circuit is increased.
It is an object of the present invention to reduce power consumption of a variable delay circuit which is capable of setting a predetermined delay time.
According to one aspect of the present invention, the variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected delayed signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are fixed (inactivated). Not operating unnecessary delay stages can prevent wasteful power consumption.
According to another aspect of the present invention, each of the delay stages has a disable terminal for stopping its operation upon receiving activation of the selecting signal corresponding to the delayed signal supplied from the previous delay stage. Further, the delay stage receiving the activated selecting signal at the disable terminal is fixed (inactivated). Since the delay stage(s) subsequent to the inactivated delay stage stop(s) its operation, wasteful power consumption can be avoided. Moreover, unnecessary delay stages are inactivated by receiving, at the disable terminal, the selecting signal used in the selector so that the variable delay circuit with low power consumption can be easily structured.
According to still another aspect of the present invention, a semiconductor integrated circuit has an adjusting circuit for adjusting an operation timing of an internal circuit. The adjusting circuit has an activation control circuit for activating any of the selecting signals. Further, the activation control circuit activates any of the selecting signals so that the delayed output signal which is the input signal delayed by a predetermined time is outputted from the variable delay circuit, thereby adjusting the operation timing of the internal circuit. Namely, an operation margin of the internal circuit is evaluated.
According to another aspect of the present invention, the adjusting circuit in the semiconductor integrated circuit has a fuse circuit for activating any of the selecting signals by blowing a fuse and a selecting circuit for validating either an activation of the selecting signal by the activation control circuit or an activation of the selecting signal by the fuse circuit. In this semiconductor integrated circuit, the selecting circuit first switches from the fuse circuit to the activation control circuit to operate the internal circuit, whereby the delayed output signal to be output at an optimal timing is determined. Next, the selecting circuit switches from the activation control circuit to the fuse circuit, and a predetermined fuse in the fuse circuit is blown so that the delayed output signal is always outputted at an optimal timing from the variable delay circuit. Namely, trimming the delayed output signal is carried out.